Optimal Temporal Partitioning and Synthesis for Recon gurable Architectures

نویسندگان

  • Meenakshi Kaul
  • Ranga Vemuri
چکیده

We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and high-level synthesis from behavioral speciications destined to be implemented on reconngurable processors. We present tight linearizations of the NLP model. We present eeective variable selection heuristics for a branch and bound solution of the derived linear programming model. We show how tight linearizations combined with good variable selection techniques during branch and bound yield optimal results in relatively short execution times.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Recon gurable Multi - FPGA Architectures ?

This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Reconngurable Computing Systems) for automatically partitioning and synthesizing designs for recon-gurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speciications at the behavior level, in the form of task graphs. The system contains a temporal par...

متن کامل

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures

This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Recon gurable Computing Systems) for automatically partitioning and synthesizing designs for recongurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speci cations at the behavior level, in the form of task graphs. The system contains a temporal part...

متن کامل

Optimal Algorithms for Constrained Recon gurable Meshes

This paper introduces a constrained recon gurable mesh model which incorporates practical assump tions about propagation delays on large sized buses Simulations of optimal recon gurable mesh algo rithms on the constrained recon gurable mesh model are found to be non optimal Optimal solutions for the sorting and convex hull problems are then presented For the problems investigated the con strain...

متن کامل

An Automated Temporal Partitioning and Loop Fission approach for FPGA based recon gurable synthesis of DSP applications

FPGA based recon gurable synthesis of DSP applications Meenakshi Kauly, Ranga Vemuriz, Sriram Govindarajan and Iyad Ouaiss Laboratory for Digital Design Environments Department of ECECS P.O. Box 210030 University of Cincinnati Cincinnati, OH 45221{0030 DAC-99 Topic M2.1 : Con gurable Computing, FPGA and rapid prototyping All appropriate organizational approvals for the publication of this paper...

متن کامل

Mapping Loops onto Reconfigurable Architectures

Recon gurable circuits and systems have evolved from application speci c accelerators to a general purpose computing paradigm. But the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. Loop statements in traditional programs consist of regular, repetitive computations which are the most likely candidates for performance enhan...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1998